library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity FIFOTest is
  port( 							
    clk, reset: in std_logic;
    i_read_O, i_write: in std_logic;
    full, empty:  out std_logic; --o_hold, 
    o_data_out: out std_logic_vector(2 downto 0);
 	words_used: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)

    );
end FIFOTest;
architecture behavior of FIFOTest is  
	component Output_FIFO
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		full		: OUT STD_LOGIC ;
		q		    : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
	);
	end component;
		
	begin
	FIFO_Data_Output_1: Output_FIFO
	Port Map (
		aclr=>'0', clock=>clk, data=>"101", rdreq=>i_read_O,
		wrreq=>i_write, empty=>empty, 
		full=>full, q=>o_data_out, usedw=>words_used 
		);

end behavior;
	